The present invention relates to flash memory arrays, and more particularly to a flash memory array having improved core field isolation in select gate regions via shallow trench isolation.
When fabricating silicon integrated circuits, devices built onto the silicon must be isolated from one another so that these devices can be subsequently interconnected to create specific circuit configurations. From this perspective, it can be seen that isolation technology is one of the critical aspects of fabricating integrated circuits.
FIG. 1A is a top view of a portion of a NAND flash memory array 10 and FIG. 1B is a corresponding circuit diagram of the flash memory array 10. The flash memory array 10 includes a core area 12 and a periphery area 14. The core area 12 includes an array of memory transistors 16 and two select gate regions that include a row of select transistors connected by a select word-line 28. One select gate region is referred to as a select drain gate region 18 and the other select gate region is referred to as a select source gate region 20. Although not shown, the periphery area 14 contains low-voltage transistors for handling logic and switching circuitry, and high-voltage transistors for handling high-voltages encountered during flash memory programming and erase operations.
The memory transistors 16 are stacked gate structures that include a layer of type-1polysilicon (poly1) 22 that form floating gates, and a layer of type-2 polysilicon (poly2) that forms word-lines 26 interconnecting a row of memory transistors 16. The select transistors in the select gate regions 18 and 20 are single gate structures comprising a layer of poly1 22, which also forms the select word-line 28 connecting the select gate transistors. Fabricating such an array is a multi-step process. For advanced deep submicrometer and high density flash memory technology, a dial field oxidation process, or LOCOS (LOCal Oxidation of Silicon), is usually required to optimize memory transistor isolation and periphery circuit isolation, respectively.
FIG. 2 is a flow chart illustrating the conventional process steps required to fabricate a NAND flash memory array 10. The first LOCOS process begins by defining active device regions and field regions in the core area 12 in step 50. The LOCOS process further includes patterning a nitride layer over the active device regions, and then using the nitride layer as a mask, growing a thin field oxide region (FOX) 30 between the active device regions using a thermal oxidation process in step 52.
After the first LOCOS process is completed, a peripheral field mask of photo resist is deposited and etched, which leaves the FOX regions 30 exposed in step 54. Then, a second LOCOS process is performed in which a thick field oxide is grown in the periphery area 14 in step 55, followed by deposition of a field implant mask in step 56. After the masking, a peripheral field implant is performed to create a field-isolation doping layer under the FOX regions 30 in step 57.
FIG. 3A is a cross-sectional view of the periphery area 14 of the flash memory showing the periphery field mask 36 and the exposed FOX regions 30. During the peripheral field implant, a dopant comprising Boron is typically implanted at a dose of approximately 5xc3x971012 atoms/cm2 at 150 keV.
Referring again to FIG. 2, after the periphery field implant, the next in the process is to deposit tunnel oxide and a layer of poly1 22 in the core and periphery areas 12 and 14 in step 58. This process results in the core area 12 having a layer of tunnel oxide 32 having a thickness of approximately 95 angstroms, and the select gate regions 18 and 20 and the periphery area having a layer of select gate oxide 34 having a thickness of approximately 180 angstroms, as shown in FIG. 1B.
After the poly1 deposition, a poly1 mask is deposited in step 60, followed by a poly1 etch in step 62. As shown in FIG. 1, the poly1 22 is etched away over the FOX regions 30, and terminates at the boundary between the core area 12 and the select gate regions 18 and 20. Because the poly1 22 serves as floating gates for the memory transistors 16 and select transistor gates as well as the select word-lines 28, the layer of poly1 22 must be continuous in the select gate regions 18 and 20 so the separate select devices can be connected together to perform their respective functions.
Referring again to FIG. 2, because of the differences in field oxide thickness between core area 12 and select gate regions 18 and 20, core isolation for a flash memory array 10, such as a NAND array, is typically achieved by performing an additional channel stop implant in the core area 12 after the poly1 etch in step 64.
FIG. 3B is a cross-sectional view of the core area 12 and the select gate region 18 and 20 during a conventional channel stop implant. As shown, the poly1 22 and the poly1 mask 38 do not cover the FOX regions 30 between the memory transistors 16, but do cover the FOX regions 30 in the select gate regions 18 and 20 since the poly1 22 forms the select word-line 28. During the channel stop implant, a dopant comprising Boron is typically implanted at a dose of approximately 1xc3x971013 atoms/cm2 at 60 keV.
Referring again to FIG. 2, after the channel stop implant, the process continues with steps such as depositing ONO (not shown) and the poly2 to form the core word-lines 26 and the select word-lines 28.
The above approach has the disadvantage that during the channel stop implant, the dopant cannot penetrate the poly1 22 and mask 38 covering the select gate regions 18 and 20. This results in very weak isolation at the select gate regions 18 and 20 (e.g. the region between the first word-line and the select drain gate 18, and the region between the last word-line and the select source gate 20). Weak isolation in the select gate regions 18 and 20 can be problematic because the word-line voltage for the NAND flash memory can go as high as 20 volts or above during programming. At the high word-line voltage, the isolation regions, especially between the edge word-lines 26 and the select gate regions may, turn on due to the lack of a channel stop implant. The result is that the select word-lines 28 are no longer isolated from the adjacent word-lines.
Accordingly, a flash memory array having improved field isolation in the select gate regions and is needed. The present invention addresses such a need.
The present invention provides a flash memory array having improved core field isolation in select gate regions via shallow trench isolation. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches in the substrate, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.
According to the preferred embodiment, using shallow trenches results in stronger isolation in the select gate regions and requires only one implant for the both the periphery and the core areas, thereby reducing the number of processing steps required to fabricate the memory array.